As the dimensions of transistors are scaled down, the reduction of vertical junction depth and suppression of dopant lateral diffusion in order to control short-channel characteristics become greater challenges. The implant of p-type dopants (impurities), such as boron, BF2, and indium is typically needed to neutralize lateral diffusion of n-type impurities (arsenic, phosphorus, etc.) from source/drain regions, and to keep the short channel effect under control.
However, it is difficult to confine the boron/BF2 within desired locations to effectively neutralize the lateral diffusion of the n-type dopants. Having high diffusibility, boron and BF2 dopants diffuse away easily from original implanted regions during subsequent processes that require elevated temperatures, such as rapid thermal annealing (RTA) steps. Therefore, the p-type dopant's ability to neutralize the n-type dopants diffused from source/drain regions is reduced.
One of the commonly used methods to effectively confine the p-type pocket/halo profile is lowering the temperatures of the RTA. The activation of the source/drain impurities, however, is affected, resulting in degraded drive current.
Other methods are also explored to reduce the diffusion and confine the profile of the dopants. U.S. Pat. No. 5,885,861 discussed a method of confining the diffusion of p-type or n-type impurities. As shown in FIG. 1, a gate electrode 6 is formed over a substrate 2. N-type dopants and p-type dopants are introduced into the gate electrode 6 and lightly diffused source/drain (LDD) regions 8 of nMOS devices and pMOS devices, respectively. Arrows 10 symbolize the implanting. For n-type devices, nitrogen and fluorine are co-implanted to the gate electrode 6 and LDD regions 8, and for p-type devices, nitrogen and carbon are co-implanted to the gate electrode 6 and LDD regions 8. Nitrogen, carbon, and fluorine have the function of retarding the diffusion of respective dopants. Therefore, the diffusion of the dopants is controlled when annealed, and thus the LDD regions 8 have higher impurity concentrations and more confined profiles.
To achieve better results, n-type impurities also need to be confined. U.S. Pat. application Ser. No. 2004/0102013 discussed a method for confining the profile of phosphorus in deep source/drain regions 16 of nMOS devices, as illustrated in FIG. 2. After the formation of a gate electrode 12 over a substrate 20, LDD regions 14 are formed by introducing an n-type dopant such as arsenic. Spacers 11 are then formed. Arrows 22 symbolize the impurity implants. Phosphorus is introduced to form deep source/drain regions 16. Carbon or fluorine is also implanted into the same regions. The addition of carbon or fluorine makes relatively high concentrations of phosphorus possible since less is diffused away, and transistor drive current is improved without unduly compromising the short channel characteristics.
However, these approaches are effective only in suppressing vertical diffusion. As a result, the junction depth is effectively controlled by the implantation of carbon/fluorine/nitrogen. The same approaches are less effective in suppressing lateral diffusion of the dopants into the channel region. A method of suppressing lateral diffusion to improve the short channel characteristics of NMOS devices, therefore, is needed.